Tags: #◇Computer Science #◇CSARCH1 #◇Digital Logic #◇Verilog #◇Reviewer #◇Finals

CSARCH1 Comprehensive Finals Reviewer

◇Overview

This reviewer consolidates Computer Organization and Digital Logic (CSARCH1). Core disciplines encompass positional base conversions, signed binary data representations (Sign-Magnitude, 1's Complement, 2's Complement), Boolean algebra theorems, Karnaugh Maps (K-Maps) minimization, combinational logic design (Adders, Multiplexers, Decoders, Encoders), sequential circuits (Latches, Flip-Flops: SR, D, JK, T), Finite State Machines (Mealy vs Moore models), state transition minimization, and Verilog Hardware Description Language (structural gate-level and behavioral modeling).

◇1. Digital Combinational & Sequential Building Blocks

Component	Function / Truth Behavior	Key Boolean Equations
Half Adder	Adds 2 single bits	$\text{Sum} = A \oplus B$ , $\text{Cout} = A B$
Full Adder	Adds 2 bits plus carry-in $Cin$	$\text{Sum} = A \oplus B \oplus Cin$ , $\text{Cout} = A B + Cin(A \oplus B)$
Multiplexer (MUX)	$2^n$ -to-1 data selector using $n$ select lines	$Y = \sum_{i=0}^{2^n-1} m_i \cdot D_i$
Decoder	$n$ -to- $2^n$ binary line decoder	Activates exactly one output line corresponding to input binary value
D Flip-Flop	Data storage on active clock edge	$Q(t+1) = D$
JK Flip-Flop	Universal storage with toggle state	$Q(t+1) = J \bar{Q} + \bar{K} Q$ (Toggles when $J=1, K=1$ )
T Flip-Flop	Binary counter toggle element	$Q(t+1) = T \oplus Q$

◇2. Moore vs Mealy Finite State Machines

Moore Machine: Outputs are associated strictly with states. Synchronous and glitch-free; often requires more states.
Mealy Machine: Outputs are associated with transitions (state + inputs). Responds one cycle faster, uses fewer states, but output can glitch with input noise.

◇3. High-Yield Exam Checklist

In $n$ -bit 2's complement, what is the valid numerical range? $-2^{n-1}$ to $2^{n-1}-1$ (e.g. 8-bit: $-128$ to $+127$ ).
How is 2's complement computed? Invert all bits and add 1.
In a K-Map, can you group cells in groups of 3 or 6? NO! Groups must strictly be powers of 2 ( $1, 2, 4, 8, 16$ ).
In Verilog, what assignment operator is used inside clocked always @(posedge clk) blocks? Non-blocking assignment <=.
For continuous combinational assignments in Verilog, what keyword is used? assign with blocking evaluation.

Previous Topic: ◇CCPROG1
Next Topic: ◇CSARCH2, ◇LBYARCH
Prerequisites: ◇Digital Logic, Boolean Algebra, Combinational/Sequential Circuits, Verilog
Cross-Curricular Connections: ◇CSOPESY

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